First-in-first-out (FIFO) circular and ring buffers are among the most commonly used building blocks in integrated circuit and microprocessor (or, chip) design for various purposes such as buffering, flow control, latency stealing, and so forth. In general, FIFO's are used to maintain in-order processing of processes and queues.
FIG. 1 shows a schematic diagram of a known system 10 implementing a FIFO buffer in RAM 20. The FIFO in RAM has a predetermined depth 2D where D is a positive integer excluding zero (i.e. D=1, 2 . . . ). Hardware FIFO's are typically implemented using read and write pointers which are used to generate read and write addresses, resulting from the read address generation function 30 and write address generation function 40 which operate in accordance with preconfigured read pointer generation logic 50 and write pointer generation logic 60, as shown in FIG. 1 Keeping track of the full and empty status of a FIFO is important because any reliable system cannot tolerate data loss or transfer of stale data. This is represented as the full and empty generation logic function 70 shown in FIG. 1.
In order to keep accurate track of full and empty status, typical read and write pointers are configured to be one bit wider than the width required to specify the FIFO read and write addresses. By using this additional most significant bit (MSB), it may be determined whether the FIFO is approaching a full state or an empty state. In typical implementations, if the read and write pointer MSB's are equal, then this is an indication that the read pointer is chasing the write pointer. Conversely, if the read and write pointer MSB's are unequal, then this is an indication that the write pointer is chasing the read pointer.
Large FIFO's are commonly implemented in random access memory (RAM). RAM chip power consumption is an ongoing concern, however, as the amount of RAM included in chips continues to grow as fabrication technologies involve smaller and smaller scales (e.g. 28 nm or 40 nm fabrication technologies). Leakage power is a dominant factor in small scale fabrication technologies and it sometimes contributes at least 20-30% of total power consumption in typical chips. The power consumed by FIFO's in many telecommunication and storage chips presents a significant disadvantage and thus needs to be addressed.
Current RAM often provides multiple power saving modes which reduce the voltage to parts of the RAM or power gate it. Different names specific to particular vendors are used to designate these different power saving modes. For example, the terms “light sleep”, “deep sleep”, and “power gating” are sometimes used. In this instance, light sleep provides the least power saving, while deep sleep provides greater power saving, and power gating provides the greatest power saving. Similarly, recovery time (time to restore to operation) from light sleep is the shortest, while deep sleep requires a longer recovery time, and power gating requires the longest recovery time.
The above modes are just examples and can vary from vendor to vendor and technology to technology. For example, ARM™ 28 nm RAM's have four modes called “selective pre-charge”, “RET1”, “RET2”, and “power gating”.
Whatever the power saving modes provided, each mode will enable power saving while using RAM in any application including FIFO, but will also introduce transition overhead. In other words, the transition from one mode to another typically consumes power. Clearly, there will be a net cost if the overhead of the transitions to and from a power saving mode is greater than the power saving gained by switching to that mode over the relevant period. In such case, it is preferable not to transition to the power saving mode, but instead to remain in the current mode.
In typical implementations of power saving modes for FIFO's implemented in RAM, the decision to enter power saving mode is based on the traffic behavior of the FIFO. For example, if there is no traffic to or from the FIFO for a certain duration, then the RAM is transitioned into one of the available power saving modes. In some cases, the selection of mode is performed on a per cycle basis. These methods are generally based on certain predictions and have a number of disadvantages.
For example, in some implementations the RAM is transitioned to a power saving mode when no traffic to the FIFO occurs within a predetermined duration. If the prediction based on the predetermined duration is incorrect, however, and traffic to the FIFO recommences at the moment the power saving mode is entered, the traffic must be stalled and the RAM returned to the normal, operational mode. As a result, performance is lost as traffic was stalled for certain duration (while transitioning from power saving mode to normal mode) and additional power is consumed as transitions between different modes consumes excess power, as noted above.
In some implementations the decision to enter a power saving mode is made on a per clock cycle basis. Transition from the power saving mode to the normal, operational mode takes time, however, including typically at least a couple of clock cycles dependent upon technology and frequency of operation. At higher clock frequencies it may not be feasible to make the decision on a per clock cycle basis as the clock period may not be sufficient to make the decision and meet the timing requirement of a mode. There are few RAM vendors having a strict sequence of steps to enter in a power saving mode and thus approaches wherein decisions are made on a per clock cycle basis may not apply.
Further methods which do not overcome the above disadvantages are disclosed in Energy-Effective Issue Logic, Daniele Folegnani and Antonio Gonzalez, 2001 IEEE; and A Robust Ultra-Low Power Asynchronous FIFO Memory With Self-Adaptive Power Control, M. Chang, P. Huang, and W. Hwang, 2008 IEEE.
In any event, and as illustrated above, methods which base the decision to enter a power saving mode on traffic prediction tend to be inefficient and suffer performance degradation and higher power consumption in certain cases.
There remains a need, therefore, of a power saving solution for FIFO's without performance degradation.